This invention relates to a field effect transistor (FET) having an active layer of a two-dimensional electronic gas layer stored at a hetero junction, and a method of fabricating it, and more particularly to an FET suited to threshold value control and gate electrode formation and a method of fabricating it.
Examples of a hetero-junction type FET are disclosed in Japanese Patent Unexamined Publication Nos. 57-7165, 57-193067, 57-118676.
An example of the hetero junction FET as shown in FIG. 1 comprises, on a semi-insulating GaAs substrate 10, an undoped or unintentionally doped GaAs 11 of about 1 .mu.m thick ("undoped" or "unintentionally doped" implies being a very weak n or p conductivity type as a result of intentionally non-doping impurities and its impurity concentration is less than 1.times.10.sup.16 cm.sup.-3, more preferably less than 1.times.10.sup.15 cm.sup.-3), an undoped or unintentionally doped Al.sub.x Ga.sub.1-x As (x.perspectiveto.0.3) layer 12 of 60 .ANG. thick, an n-type Al.sub.x Ga.sub.1-x As (x.perspectiveto.0.3) layer 13 of 400 .ANG., and an n-type GaAs layer 14 of 200 .ANG., which are successively formed by crystal growth of an MBE (Molecular Beam Epitaxy) or OM-VPE method (Organic Metal Vapor Phase Deposition), and a gate electrode 15 and source-drain electrode 16, 16' formed after the crystal growth. In forming an enhancement type FET (E-FET) and/or a depletion type FET (D-FET) in one and the same substrate, the enhancement type FET has been hitherto formed in a manner of selectively etching the uppermost n-type GaAs layer 14 through dryetahing method and depositing on the Al.sub.x Ga.sub.1-x As layer 13 thus exposed a gate metallic electrode 15'.
A band structure at a cross section of the prior art D-FET type hetero junction FET is shown in FIG. 4. In the figure, numeral 15 denotes a gate electrode part, 13 denotes an AlGaAs layer containing door impurities, and 11 denotes an undoped GaAs layer substantially not containing impurities. The undoped GaAlAs layer 12 provides for increasing the mobility but is omitted for simplicity of illustration. E.sub.F designates the Fermi level. At the hetero interface, a potential well is provided due to the difference of electron affinity and two-dimensional carriers occur therein. These carriers 21 are supplied from the donor level 41 in the AlGaAs layer 13, and this donor level 41 and the two dimensional carriers 21 are in a thermal equilibrium state. Because the carriers 21 move through the GaAs layer 11 substantially not containing impurities, and are spatially separated from ionized donor impurities, dispersion thereof due to the impurity potential is greatly reduced, realizing a higher mobility inherent to GaAs. Thus, this prior art hetero junction FET has drawn attention from the viewpoint of the application to a high speed transistor.
However, despite of all the hoopla over the possibility of realization of a higher mobility, structural and technical problems associated with this hetero junction type FET have not been discussed much.
A first problem encountered in implementing a high-speed high-degree integrated circuit using these hetero junction type FET's is a method of controlling a threshold voltage V.sub.Th and a technique, directly associated therewith, of individually providing E-FET's and D-FET's in a common substrate.
The above-mentioned method of forming E/D FET's has posed a problem of deteriorating the Al.sub.x Ga.sub.1-x As layer due to injury by dry etching, making it impossible to form gate electrodes of good quality.
Moreover, GaAs and Al.sub.x Ga.sub.1-x As are very active in their surface so that when they are exposed to air through impurities, oxidation, etc., they are immediately contaminated, thereby preventing proper gate electrode formation.
On the other hand, the threshold voltage V.sub.Th of this FET (E-FET here) can be represented, omitting terms originating from the undoped GaAs layer, as follows: ##EQU1## where .phi..sub.Bn is a height of a Schottky barrier at the gate electrode, .DELTA.E.sub.c is energy discontinuity amount of a conduction band, at the hetero junction part, q is a unit charge, .epsilon. is a permittivity, N.sub.D is a donor doping concentration, and d is a film thickness of the n-type AlGaAs layer.
Meanwhile, the greatest problem encountered in applying this FET to an integrated circuit (IC) is control of the threshold voltage of the E-FET. The application of the MBE or OM-VPE method provides nonuniformity of film thickness among production lots and greatly reduces production yield in the IC. Thus, in the application of the FET to the IC, the above film thickness d must be controlled within a range of 15 .ANG. as understood from equation (1).
In short, the problems associated with the above prior art FET reside in the following two points:
1. The threshold voltage V.sub.Th has previously determined at the time of crystal growth.
2. Since the gate electrodes are formed after the exposure to air following the crystal growth, defective gate electrodes are liable to be formed.